Mahesh M, Nalesh S, Kala S. Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGA. In Gang Qu 0001, Jinjun Xiong, Danella Zhao, Venki Muthukumar, Md Farhadur Reza, Ramalingam Sridhar, editors, 34th IEEE International System-on-Chip Conference, SOCC 2021, Las Vegas, NV, USA, September 14-17, 2021. pages 7-12, IEEE, 2021. [doi]
Abstract is missing.