Table of Contents

• Implementation and Evaluation of a Neural Network-Based LiDAR Histogram Processing Method on FPGAGongbo Chen, Giray Atabey Kirtiz, Christian Wiede, Rainer Kokozinski. 1-6 [doi]
• Bandwidth-Efficient Sparse Matrix Multiplier Architecture for Deep Neural Networks on FPGAMahesh M, Nalesh S, Kala S. 7-12 [doi]
• Tufan: Low-Power Throughput Architecture for Acceleration of EfficientNet on Cloud FPGAsMohammadreza Baharani, Ushma Sunil Bharucha, Kaustubh Manohar Mhatre, Hamed Tabkhi. 13-18 [doi]
• Optimizing Quantum Circuits for Arbitrary State Synthesis and InitializationNaveed Mahmud, Andrew MacGillivray, Manu Chaudhary, Esam El-Araby. 19-24 [doi]
• Optimization of 3D Stacked Nanosheets in 5nm Gate-all-around Transistor TechnologyAnil Kumar Gundu, Volkan Kursun. 25-28 [doi]
• Dual-Band GSM Energy Harvester for a Duty-Cycle Approach in 180nm CMOS TechnologyHugo D. Hernandez, Diego Augusto Pontes, Bruno Soares, Dionisio de Carvalho, Wilhelmus A. M. Van Noije. 29-33 [doi]
• Stereolithography-Based Rectenna for Wireless Energy HarvestingXuan Viet Linh Nguyen, Tony Gerges, Jean-Marc Duchamp, Philippe Benech, Jacques Verdier, Philippe Lombard, Michel Cabrera, Bruno Allard. 34-39 [doi]
• Software-defined Temporal Decoupling in Virtual PlatformsLukas Jünger 0001, Alexander Belke, Rainer Leupers. 40-45 [doi]
• Embedded ICG-based Stroke Volume Measurement System: Comparison of Discrete-Time and Continuous-Time ArchitecturesAntoine Gautier 0003, Benoît Larras, Olev Märtens, Deepu John, Antoine Frappé. 46-51 [doi]
• Analysis of the Sub-µA Fully Integrated NMOS LDO for Backscattering SystemPuYang Zheng, Xiao Sha, Milutin Stanacevic. 52-56 [doi]
• A SiPM Based Sensor For Nuclear Detection ApplicationsShahram Hatefi Hesari, Nicole McFarlane. 57-62 [doi]
• A Design Approach to Reduce Test Time on SOC MemoriesProkash Ghosh, Dieu Van Dinh, Misal Varma. 63-66 [doi]
• LC-Physical Unclonable Function in Wireless 3D IC for Securing Internet of Things DevicesJaya Dofe, Wafi Danesh. 67-70 [doi]
• Reinforcement Learning-based Power Management Architecture for Optimal DVFS in SoCsDavid Akselrod. 71-74 [doi]
• An Efficient Capsule Network Reconfigurable Hardware Accelerator for Deciphering Ancient Scripts with Scarce AnnotationsRodrigue Rizk, Dominick Rizk, Frederic Rizk, Ashok Kumar 0001, Magdy A. Bayoumi. 75-78 [doi]
• A Cost-Efficient Reversible-Based Configurable Ring Oscillator Physical Unclonable FunctionDominick Rizk, Rodrigue Rizk, Frederic Rizk, Ashok Kumar 0001, Magdy A. Bayoumi. 79-82 [doi]
• FLECSim-SoC: A Flexible End-to-End Co-Design Simulation Framework for System on ChipsTim Hotfilter, Julian Höfer, Fabian Kreß, Fabian Kempf, Jürgen Becker 0001. 83-88 [doi]
• Generating hardware and software for RISC-V cores generated with Rocket Chip generatorSüleyman Savas, Endri Bezati, Jörn W. Janneck. 89-94 [doi]
• Implementation of an SoC architecture with built-in safety featuresTibor Gergely Markovits, Péter Arató, György Rácz. 95-100 [doi]
• Power Swapper: Approximate Functional Block Assisted Cryptosystem SecurityAbhijitt Dhavlle, Setareh Rafatirad, Houman Homayoun, Sai Manoj Pudukotai Dinakarrao. 101-105 [doi]
• TestQuBE: A Testbench Enhancement Methodology for Universal Serial Interfaces in Complex SoCsAditya Kulkarni, Ayush Singh, Sachin Arun Waje, Sunil Shrirangrao Kashide, Seonil Brian Choi. 106-111 [doi]
• Performance Optimization of p-Channel SnO Cylindrical Thin Film Transistors (CTFT) Using 3D ModellingViswanath G. Akkili, Viranjay M. Srivastava. 112-116 [doi]
• 1.81 kHz Relaxation Oscillator With Forward Bias Comparator and Leakage Current Compensation Based TechniquesXiao Sha, PuYang Zheng, Milutin Stanacevic. 117-122 [doi]
• Taskrunner: A Flexible Framework Optimized for Low Latency Quantum Computing ExperimentsRichard Gebauer, Nick Karcher, Jonas Hurst, Marc Weber, Oliver Sander. 123-128 [doi]
• Total Variation Reduction for Lossless Compression of HPC ApplicationsJunqi Wang, Yida Li, Qing Liu 0002, Huizhang Luo, Kenli Li. 129-134 [doi]
• Can We Trust Machine Learning for Electronic Design Automation?Kang Liu 0017, Jeff Jun Zhang, Benjamin Tan 0001, Dan Feng. 135-140 [doi]
• Efficient Localization of Origins of PVC based on Random Signal SegmentationDawei Li, Cong Liu, Xiaowei Xu 0004. 141-145 [doi]
• On Reduction of Computations for Threshold Function IdentificationWen-Chih Hsu, Chia-Chun Lin, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang. 146-151 [doi]
• Design and Optimization of a Pruning-Efficient DCNN Inference AcceleratorChe-Hao Chang, Chih-Tsun Huang. 152-157 [doi]
• Real-Time FPGA-Based Binocular Stereo Vision System with Semi-Global Matching AlgorithmZhuoyu Chen, Pingcheng Dong, Zhuoao Li, Ruoheng Yao, Yunhao Ma, Xiwei Fang, Huanshihong Deng, Wenyue Zhang, Lei Chen, Fengwei An. 158-163 [doi]
• Key-based Obfuscation using HT-like Trigger Circuit for 128-bit AES Hardware IP CoreSurbhi Chhabra, Kusum Lata. 164-169 [doi]
• Identifying Specious LUTs for Satisfiability Don't Care Trojan DetectionLingjuan Wu, Xuefei Li, Jiacheng Zhu, Jian Zheng, Wei Hu 0008. 170-175 [doi]
• ReCPE: A PE for Reconfigurable Lightweight CryptographyJeff Anderson, Yousra Alkabani, Tarek A. El-Ghazawi. 176-181 [doi]
• Dynamic Power Analysis of Standard-Cell FPGA FabricsBo Bao, Jason Anderson. 182-187 [doi]
• A Framework for Evaluation of Debug Path Performance in SoCProkash Ghosh, Khwahish Sinha. 188-193 [doi]
• On the stability, transient and quiescent current control of one low-voltage class-AB op-amp architectureAniruddha Roy, Khyati Bansal, Nitin Agarwal. 194-199 [doi]
• Analog-Inspired Hardware Security: A Low-Energy Solution for IoT Trusted CommunicationsSamuel Ellicott, Michael Kines, Waleed Khalil, Yu Qi, Abdullah Kurtoglu, Hossein Miri Lavasani. 200-205 [doi]
• LDO-based Odometer to Combat IC RecyclingRabin Yu Acharya, Michael Valentin Levin, Domenic Forte. 206-211 [doi]
• Distributed On-Chip Power Supply for Security Enhancement in Multicore NoCXingye Liu, Paul Ampadu. 212-217 [doi]
• A Two-Stage Path Planning Engine for Robot Navigation SystemYu-En Hsu, Yen-Chin Liao, Hsie-Chia Chang. 218-223 [doi]
• An IMU-aided Fitness SystemYi-Ting Lin, Chun-Jui Chen, Pei-Yi Kuo, Si-Huei Lee, Chia-Chun Lin, Yun-Ju Lee, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang. 224-229 [doi]
• Cluster Tool Performance Analysis using Graph DatabaseShiuan-Hau Huang, Hsin-Ping Yen, Yan-Hsiu Liu, Kuang-Hsien Tseng, Ji-Fu Kung, Chia-Chun Lin, Yi-Ting Li, Yung-Chih Chen, Chun-Yao Wang. 230-235 [doi]
• NeuroVP: A System-Level Virtual Platform for Integration of Neuromorphic AcceleratorsMelvin Galicia, Ali BanaGozar, Karl J. X. Sturm, Felix Staudigl, Sander Stuijk, Henk Corporaal, Rainer Leupers. 236-241 [doi]
• FPNA: A Reconfigurable Accelerator for AI Inference at the EdgePeter Gadfort, Oluseyi A. Ayorinde. 242-247 [doi]
• Ant Colony Optimization Based NoCs for Flexible Spatial Isolation in Mixed Criticality SystemsNidhi Anantharajaiah, Felix Knopf, Jürgen Becker 0001. 248-253 [doi]
• Design Study on Impact of Memory Access Parallelism for Cloud FPGAsArnab A. Purkayastha, Hamed Tabkhi. 254-259 [doi]
• Combined Side-Channel Attacks on a Lightweight Prince Cipher ImplementationSoner Seçkiner, Selçuk Köse. 260-265 [doi]
• A Convolutional Neural Network on Chip Design Methodology for CNN Hardware ImplementationKun-Chih Jimmy Chen, Yi-Sheng Liao, Cheng-Kang Tsai. 266-271 [doi]
• Evaluating the Impact of Fault-Tolerance Capability of Deep Neural Networks Caused by FaultsYung-Yu Tsai, Jin-Fu Li. 272-277 [doi]
• A Hierarchical and Reconfigurable Process Element Design for Quantized Neural NetworksYu-Guang Chen, Chi-Wei Hsu, Hung Yi Chiang, Tsung-Han Hsieh, Jing-Yang Jou. 278-283 [doi]