Hardware-accelerated Response Time Analysis for priority-preemptive Networks-on-Chip - researchr publication related

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Yunfeng Ma, Leandro Soares Indrusiak. Hardware-accelerated Response Time Analysis for priority-preemptive Networks-on-Chip. In 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2015, Bremen, Germany, June 29 - July 1, 2015. pages 1-8, IEEE, 2015. [doi]

The following publications are possibly variants of this publication:

Hardware-accelerated evolutionary hard real-time task mapping for wormhole network-on-chip with priority-preemptive arbitrationYunfeng Ma. PhD thesis, University of York, UK, 2016. [doi]

Hardware-accelerated analysis of real-time Networks-on-ChipYunfeng Ma, Leandro Soares Indrusiak. mam, 53:81-91, 2017. [doi]

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