Erik MacLean, Vijay K. Jain. Analog Design for a Power Transmission Line Sensing and Analysis VLSI Chip. In 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010. pages 438-446, IEEE Computer Society, 2010. [doi]
@inproceedings{MacLeanJ10,
title = {Analog Design for a Power Transmission Line Sensing and Analysis VLSI Chip},
author = {Erik MacLean and Vijay K. Jain},
year = {2010},
doi = {10.1109/DFT.2010.58},
url = {http://doi.ieeecomputersociety.org/10.1109/DFT.2010.58},
researchr = {https://researchr.org/publication/MacLeanJ10},
cites = {0},
citedby = {0},
pages = {438-446},
booktitle = {25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, October 6-8, 2010},
publisher = {IEEE Computer Society},
isbn = {978-1-4244-8447-8},
}