A Parallel Scheme for Implementing Multialphabet Arithmetic Coding in High-Speed Programmable Hardware

S. Mahapatra, Kuldeep Singh. A Parallel Scheme for Implementing Multialphabet Arithmetic Coding in High-Speed Programmable Hardware. In International Symposium on Information Technology: Coding and Computing (ITCC 2005), Volume 1, 4-6 April 2005, Las Vegas, Nevada, USA. pages 79-84, IEEE Computer Society, 2005. [doi]

Abstract

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