Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features

Amitava Majumdar, Balakrishna Jayadev. Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features. In 27th IEEE Asian Test Symposium, ATS 2018, Hefei, China, October 15-18, 2018. pages 36-41, IEEE, 2018. [doi]

Authors

Amitava Majumdar

This author has not been identified. Look up 'Amitava Majumdar' in Google

Balakrishna Jayadev

This author has not been identified. Look up 'Balakrishna Jayadev' in Google