Amitava Majumdar, Balakrishna Jayadev. Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features. In 27th IEEE Asian Test Symposium, ATS 2018, Hefei, China, October 15-18, 2018. pages 36-41, IEEE, 2018. [doi]
@inproceedings{MajumdarJ18-0,
title = {Handling Clock-Domain Crossings in Dual Clock-Edge Logic for DFx Features},
author = {Amitava Majumdar and Balakrishna Jayadev},
year = {2018},
doi = {10.1109/ATS.2018.00018},
url = {https://doi.org/10.1109/ATS.2018.00018},
researchr = {https://researchr.org/publication/MajumdarJ18-0},
cites = {0},
citedby = {0},
pages = {36-41},
booktitle = {27th IEEE Asian Test Symposium, ATS 2018, Hefei, China, October 15-18, 2018},
publisher = {IEEE},
isbn = {978-1-5386-9466-4},
}