The following publications are possibly variants of this publication:
- Partitioning VLSI Floorplans by Staircase Channels for Global RoutingSubhashis Majumder, Subhas C. Nandy, Bhargab B. Bhattacharya. vlsid 1998: 59-64 [doi]
- A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase CutsBapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal. vdat 2012: 327-336 [doi]
- A New Method for Defining Monotone Staircases in VLSI FloorplansBapi Kar, Susmita Sur-Kolay, Chittarnjan Mandal. isvlsi 2015: 107-112 [doi]
- On Finding A Staircase Channel With Minimum Crossing Nets In A VLSI FloorplanSubhashis Majumder, Subhas C. Nandy, Bhargab B. Bhattacharya. jcsc, 13(5):1019-1038, 2004. [doi]