Mehrdad Majzoobi, Eva L. Dyer, Ahmed Elnably, Farinaz Koushanfar. Rapid FPGA delay characterization using clock synthesis and sparse sampling. In Ron Press, Erik H. Volkerink, editors, 2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010. pages 457-466, IEEE, 2010. [doi]
@inproceedings{MajzoobiDEK10,
title = {Rapid FPGA delay characterization using clock synthesis and sparse sampling},
author = {Mehrdad Majzoobi and Eva L. Dyer and Ahmed Elnably and Farinaz Koushanfar},
year = {2010},
doi = {10.1109/TEST.2010.5699248},
url = {http://dx.doi.org/10.1109/TEST.2010.5699248},
researchr = {https://researchr.org/publication/MajzoobiDEK10},
cites = {0},
citedby = {0},
pages = {457-466},
booktitle = {2011 IEEE International Test Conference, ITC 2010, Austin, TX, USA, November 2-4, 2010},
editor = {Ron Press and Erik H. Volkerink},
publisher = {IEEE},
isbn = {978-1-4244-7206-2},
}