Yashwant K. Malaiya, Ramesh Narayanaswamy. Modeling and Testing for Timing Faults in Synchronous Sequential Circuits. IEEE Design & Test of Computers, 1(4):62-74, 1984. [doi]
@article{MalaiyaN84,
title = {Modeling and Testing for Timing Faults in Synchronous Sequential Circuits},
author = {Yashwant K. Malaiya and Ramesh Narayanaswamy},
year = {1984},
doi = {10.1109/MDT.1984.5005692},
url = {https://doi.org/10.1109/MDT.1984.5005692},
researchr = {https://researchr.org/publication/MalaiyaN84},
cites = {0},
citedby = {0},
journal = {IEEE Design & Test of Computers},
volume = {1},
number = {4},
pages = {62-74},
}