Sanjiv Kumar Mangal, Raghavendra B. Deshmukh, Rahul M. Badghare, R. M. Patrikar. FPGA Implementation of Low Power Parallel Multiplier. In 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India. pages 115-120, IEEE Computer Society, 2007. [doi]
@inproceedings{MangalDBP07,
title = {FPGA Implementation of Low Power Parallel Multiplier},
author = {Sanjiv Kumar Mangal and Raghavendra B. Deshmukh and Rahul M. Badghare and R. M. Patrikar},
year = {2007},
doi = {10.1109/VLSID.2007.85},
url = {http://doi.ieeecomputersociety.org/10.1109/VLSID.2007.85},
researchr = {https://researchr.org/publication/MangalDBP07},
cites = {0},
citedby = {0},
pages = {115-120},
booktitle = {20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India},
publisher = {IEEE Computer Society},
isbn = {0-7695-2502-4},
}