Salvador Manich, L. Garcia-Deiros, Joan Figueras. Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources. IEEE Trans. on CAD of Integrated Circuits and Systems, 26(11):2046-2058, 2007. [doi]
@article{ManichGF07,
title = {Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources},
author = {Salvador Manich and L. Garcia-Deiros and Joan Figueras},
year = {2007},
doi = {10.1109/TCAD.2007.906465},
url = {http://dx.doi.org/10.1109/TCAD.2007.906465},
tags = {testing},
researchr = {https://researchr.org/publication/ManichGF07},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {26},
number = {11},
pages = {2046-2058},
}