The following publications are possibly variants of this publication:
- An optically-enabled chip-multiprocessor architecture using a single-level shared optical cache memoryP. Maniotis, Savvas Gitzenis, Leandros Tassiulas, Nikos Pleros. osn, 22:54-68, 2016. [doi]
- A novel chip-multiprocessor architecture with optically interconnected shared L1 optical cache memoryPavlos Maniotis, Savvas Gitzenis, Leandros Tassiulas, Nikos Pleros. ofc 2014: 1-3 [doi]
- WDM-enabled optical RAM and optical cache memory architectures for Chip MultiprocessorsTheoni Alexoudi, Dimitrios Fitsios, Pavlos Maniotis, Chris Vagionas, Sotirios Papaioannou, Amalia N. Miliou, George T. Kanellos, Nikos Pleros. icton 2015: 1-4 [doi]
- A 16GHz optical cache memory architecture for set-associative mapping in chip multiprocessorsPavlos Maniotis, D. Fitsios, George T. Kanellos, Nikos Pleros. ofc 2014: 1-3 [doi]