P-channel logic 2 T eDRAM macro with high retention bit architecture

Sivasundar Manisankar, Yeonbae Chung. P-channel logic 2 T eDRAM macro with high retention bit architecture. I. J. Circuit Theory and Applications, 46(7):1416-1425, 2018. [doi]

Authors

Sivasundar Manisankar

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Yeonbae Chung

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