Sivasundar Manisankar, Yeonbae Chung. P-channel logic 2 T eDRAM macro with high retention bit architecture. I. J. Circuit Theory and Applications, 46(7):1416-1425, 2018. [doi]
@article{ManisankarC18,
title = {P-channel logic 2 T eDRAM macro with high retention bit architecture},
author = {Sivasundar Manisankar and Yeonbae Chung},
year = {2018},
doi = {10.1002/cta.2496},
url = {https://doi.org/10.1002/cta.2496},
researchr = {https://researchr.org/publication/ManisankarC18},
cites = {0},
citedby = {0},
journal = {I. J. Circuit Theory and Applications},
volume = {46},
number = {7},
pages = {1416-1425},
}