Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow

Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown. Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. VLSI Syst., 15(8):895-903, 2007. [doi]

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