Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown. Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. VLSI Syst., 15(8):895-903, 2007. [doi]
@article{ManohararajahCSB07,
title = {Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow},
author = {Valavan Manohararajah and Gordon R. Chiu and Deshanand P. Singh and Stephen Dean Brown},
year = {2007},
doi = {10.1109/TVLSI.2007.900744},
url = {http://dx.doi.org/10.1109/TVLSI.2007.900744},
tags = {data-flow},
researchr = {https://researchr.org/publication/ManohararajahCSB07},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {15},
number = {8},
pages = {895-903},
}