Roberto Ramírez Marín, Andrés David García García, Luis Fernando González Pérez, Javier Eduardo González Villarruel. Hardware Architecture of MAP Algorithm for Turbo Codes Implemented in a FPGA. In 15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005 - 2 March 2005, Puebla, Mexico. pages 70-75, IEEE Computer Society, 2005. [doi]
@inproceedings{MarinGPV05,
title = {Hardware Architecture of MAP Algorithm for Turbo Codes Implemented in a FPGA},
author = {Roberto Ramírez Marín and Andrés David García García and Luis Fernando González Pérez and Javier Eduardo González Villarruel},
year = {2005},
url = {http://csdl.computer.org/comp/proceedings/conielecomp/2005/2283/00/22830070abs.htm},
tags = {architecture},
researchr = {https://researchr.org/publication/MarinGPV05},
cites = {0},
citedby = {0},
pages = {70-75},
booktitle = {15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005 - 2 March 2005, Puebla, Mexico},
publisher = {IEEE Computer Society},
isbn = {0-7695-2283-1},
}