A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing - researchr publication authors

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Parisa Mashreghi-Moghadamy, Tarek Ould-Bachirz, Yvon Savariay. A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing. In IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022. pages 672-676, IEEE, 2022. [doi]

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