Parisa Mashreghi-Moghadamy, Tarek Ould-Bachirz, Yvon Savariay. A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing. In IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022. pages 672-676, IEEE, 2022. [doi]
@inproceedings{Mashreghi-Moghadamy22,
title = {A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing},
author = {Parisa Mashreghi-Moghadamy and Tarek Ould-Bachirz and Yvon Savariay},
year = {2022},
doi = {10.1109/ISCAS48785.2022.9937607},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937607},
researchr = {https://researchr.org/publication/Mashreghi-Moghadamy22},
cites = {0},
citedby = {0},
pages = {672-676},
booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2022, Austin, TX, USA, May 27 - June 1, 2022},
publisher = {IEEE},
isbn = {978-1-6654-8485-5},
}