A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOS Using a Tri-State Binary PD with 100ps Gated Digital Output - researchr publication authors

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Takashi Masuda, Hideyuki Suzuki, Hiroshi Iizuka, Akio Igarashi, Kaneyoshi Takeshita, Takayuki Mogi, Takayuki Shoji, Jeremy Chatwin, Iain Butler, Derek Mellor. A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOS Using a Tri-State Binary PD with 100ps Gated Digital Output. In 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. pages 438-614, IEEE, 2007. [doi]

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