Takashi Masuda, Hideyuki Suzuki, Hiroshi Iizuka, Akio Igarashi, Kaneyoshi Takeshita, Takayuki Mogi, Takayuki Shoji, Jeremy Chatwin, Iain Butler, Derek Mellor. A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOS Using a Tri-State Binary PD with 100ps Gated Digital Output. In 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. pages 438-614, IEEE, 2007. [doi]
@inproceedings{MasudaSIITMSCBM07,
title = {A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOS Using a Tri-State Binary PD with 100ps Gated Digital Output},
author = {Takashi Masuda and Hideyuki Suzuki and Hiroshi Iizuka and Akio Igarashi and Kaneyoshi Takeshita and Takayuki Mogi and Takayuki Shoji and Jeremy Chatwin and Iain Butler and Derek Mellor},
year = {2007},
doi = {10.1109/ISSCC.2007.373482},
url = {http://dx.doi.org/10.1109/ISSCC.2007.373482},
researchr = {https://researchr.org/publication/MasudaSIITMSCBM07},
cites = {0},
citedby = {0},
pages = {438-614},
booktitle = {2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007},
publisher = {IEEE},
isbn = {1-4244-0853-9},
}