Design and implementation of a 5×5 trits multiplier in a quasi-adiabatic ternary CMOS logic

Diego Mateo, Antonio Rubio. Design and implementation of a 5×5 trits multiplier in a quasi-adiabatic ternary CMOS logic. J. Solid-State Circuits, 33(7):1111-1116, 1998. [doi]

Abstract

Abstract is missing.