Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs

Anmol Mathur, C. L. Liu. Timing Driven Placement Reconfiguration for Fault Tolerance and Yield Enhancement in FPGAs. In 1996 European Design and Test Conference, ED&TC 1996, Paris, France, March 11-14, 1996. pages 165-169, IEEE Computer Society, 1996. [doi]

References

No references recorded for this publication.

Cited by

No citations of this publication recorded.