Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs

Chizu Matsumoto, Yuichi Hamamura, Michinobu Nakao, Kaname Yamasaki, Yoshikazu Saito, Shun'ichi Kaneko. Novel Fuse Scheme with a Short Repair Time to Maximize Good Chips per Wafer in Advanced SoCs. IEICE Transactions, 96-C(1):108-114, 2013. [doi]

Authors

Chizu Matsumoto

This author has not been identified. Look up 'Chizu Matsumoto' in Google

Yuichi Hamamura

This author has not been identified. Look up 'Yuichi Hamamura' in Google

Michinobu Nakao

This author has not been identified. Look up 'Michinobu Nakao' in Google

Kaname Yamasaki

This author has not been identified. Look up 'Kaname Yamasaki' in Google

Yoshikazu Saito

This author has not been identified. Look up 'Yoshikazu Saito' in Google

Shun'ichi Kaneko

This author has not been identified. Look up 'Shun'ichi Kaneko' in Google