An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology

Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata. An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology. IEICE Transactions, 93-C(6):820-826, 2010. [doi]

@article{MatsunoFKHTSN10,
  title = {An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology},
  author = {Tetsuro Matsuno and Daisuke Fujimoto and Daisuke Kosaka and Naoyuki Hamanishi and Ken Tanabe and Masazumi Shiochi and Makoto Nagata},
  year = {2010},
  url = {http://search.ieice.org/bin/summary.php?id=e93-c_6_820},
  researchr = {https://researchr.org/publication/MatsunoFKHTSN10},
  cites = {0},
  citedby = {0},
  journal = {IEICE Transactions},
  volume = {93-C},
  number = {6},
  pages = {820-826},
}