Notice of Violation of IEEE Publication Principles: A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation

Adrian Maxim. Notice of Violation of IEEE Publication Principles: A 0.16-2.55-GHz CMOS active clock deskewing PLL using analog phase interpolation. J. Solid-State Circuits, 40(1):110-131, 2005. [doi]

Abstract

Abstract is missing.