Hugh McIntyre, Dennis Wendell, K. James Lin, P. Kaushik, Suresh Seshadri, Alfred Wang, V. Sundararaman, Ping Wang, Song Kim, Wen-Jay Hsu, Hee-Choul Park, Gideon Levinsky, Jiejun Lu, M. Chirania, Raymond A. Heald, Paul Lazar, Sanjaya Dharmasena. A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor. J. Solid-State Circuits, 40(1):52-59, 2005. [doi]
@article{McIntyreWLKSWSW05,
title = {A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor},
author = {Hugh McIntyre and Dennis Wendell and K. James Lin and P. Kaushik and Suresh Seshadri and Alfred Wang and V. Sundararaman and Ping Wang and Song Kim and Wen-Jay Hsu and Hee-Choul Park and Gideon Levinsky and Jiejun Lu and M. Chirania and Raymond A. Heald and Paul Lazar and Sanjaya Dharmasena},
year = {2005},
doi = {10.1109/JSSC.2004.838017},
url = {https://doi.org/10.1109/JSSC.2004.838017},
researchr = {https://researchr.org/publication/McIntyreWLKSWSW05},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {40},
number = {1},
pages = {52-59},
}