Gate-level netlist reverse engineering for hardware security: Control logic register identification

Travis Meade, Yier Jin, Mark Tehranipoor, Shaojie Zhang. Gate-level netlist reverse engineering for hardware security: Control logic register identification. In IEEE International Symposium on Circuits and Systems, ISCAS 2016, Montréal, QC, Canada, May 22-25, 2016. pages 1334-1337, IEEE, 2016. [doi]

Abstract

Abstract is missing.