Scalable Multistage Network for Multiprocessor System-on-Chip Design - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Samy Meftali, Jean-Luc Dekeyser, Isaac D. Scherson. Scalable Multistage Network for Multiprocessor System-on-Chip Design. In 8th International Symposium on Parallel Architectures, Algorithms, and Networks, ISPAN 2005, December 7-9. 2005, Las Vegas, Nevada, USA. pages 352-357, IEEE Computer Society, 2005. [doi]

This author has not been identified. Look up 'Samy Meftali' in GoogleThis author has not been identified. Look up 'Jean-Luc Dekeyser' in GoogleThis author has not been identified. Look up 'Isaac D. Scherson' in Google

runs on WebDSL