Samy Meftali, Jean-Luc Dekeyser, Isaac D. Scherson. Scalable Multistage Network for Multiprocessor System-on-Chip Design. In 8th International Symposium on Parallel Architectures, Algorithms, and Networks, ISPAN 2005, December 7-9. 2005, Las Vegas, Nevada, USA. pages 352-357, IEEE Computer Society, 2005. [doi]
@inproceedings{MeftaliDS05,
title = {Scalable Multistage Network for Multiprocessor System-on-Chip Design},
author = {Samy Meftali and Jean-Luc Dekeyser and Isaac D. Scherson},
year = {2005},
doi = {10.1109/ISPAN.2005.77},
url = {http://doi.ieeecomputersociety.org/10.1109/ISPAN.2005.77},
tags = {design},
researchr = {https://researchr.org/publication/MeftaliDS05},
cites = {0},
citedby = {0},
pages = {352-357},
booktitle = {8th International Symposium on Parallel Architectures, Algorithms, and Networks, ISPAN 2005, December 7-9. 2005, Las Vegas, Nevada, USA},
publisher = {IEEE Computer Society},
}