A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS

Mohamed Megahed, Tejasvi Anand. A Sub-μW Energy Harvester Architecture With Reduced Top/Bottom Plate Switching Loss Achieving 80.66% Peak Efficiency in 180-nm CMOS. J. Solid-State Circuits, 58(5):1386-1399, May 2023. [doi]

Abstract

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