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High-performance noise tolerant comparator design for arithmetic circuits

Preetisudha Meher, Kamala Kanta Mahapatra. High-performance noise tolerant comparator design for arithmetic circuits. In International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2016, Phuket, Thailand, October 24-27, 2016. pages 1-4, IEEE, 2016. [doi]

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Preetisudha Meher

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Kamala Kanta Mahapatra

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