Hierarchical layout verification for submicron designs - researchr publication authors

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W. Meier. Hierarchical layout verification for submicron designs. In Gordon Adshead, Jochen A. G. Jess, editors, European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990. pages 382-386, IEEE Computer Society, 1990. [doi]

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