Limits of gate-level power estimation considering real delay effects and glitches

Michael Meixner, Tobias G. Noll. Limits of gate-level power estimation considering real delay effects and glitches. In Jari Nurmi, Peeter Ellervee, Dragomir Milojevic, Ondrej Daniel, Tommi Paakki, editors, 2014 International Symposium on System-on-Chip, SoC 2014, Tampere, Finland, October 28-29, 2014. pages 1-7, IEEE, 2014. [doi]

Abstract

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