Abstract is missing.
- I/O virtualization utilizing an efficient hardware system-level Memory Management UnitGeorge Kornaros, Konstantinos Harteros, Ioannis Christoforakis, Maria Astrinaki. 1-4 [doi]
- A Reconfigurable MapReduce accelerator for multi-core all-programmable SoCsChristoforos Kachris, Georgios Ch. Sirakoulis, Dimitrios Soudris. 1-6 [doi]
- Optimal data path widths for energy- and area-efficient Max-Log-MAP based LTE Turbo decodersMartin Broich, Tobias G. Noll. 1-8 [doi]
- Early power-aware Design Space Exploration for embedded systems: MPEG-2 case studyFeriel Ben Abdallah, Chiraz Trabelsi, Rabie Ben Atitallah, Mourad Abed. 1-8 [doi]
- A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecturePei Liu, Ahmed Hemani, Kolin Paul. 1-8 [doi]
- Gamification of System-on-Chip designTimo D. Hämäläinen, Erno Salminen. 1-8 [doi]
- Keyed logic BIST for Trojan detection in SoCElena Dubrova, Mats Näslund, Gunnar Carlsson, Ben J. M. Smeets. 1-4 [doi]
- A transaction-level framework for design-space exploration of hardware-enhanced operating systemsDaniel Gregorek, Alberto García Ortiz. 1-4 [doi]
- Limits of gate-level power estimation considering real delay effects and glitchesMichael Meixner, Tobias G. Noll. 1-7 [doi]
- Formal verification of circuit-switched Network on chip (NoC) architectures using SPINAnam Zaman, Osman Hasan. 1-8 [doi]
- A cycle-accurate Network-on-Chip simulator with support for abstract task graph modelingJan Moritz Joseph, Thilo Pionteck. 1-6 [doi]
- A communication model and partitioning algorithm for streaming applications for an embedded MPSoCWayne Kelly, Martin Flasskamp, Gregor Sievers, Johannes Ax, Jianing Chen, Christian Klarhorst, Christoph Ragg, Thorsten Jungeblut, Andrew Sorensen. 1-6 [doi]
- An implementation of Auto-Memoization mechanism on ARM-based superscalar processorYuuki Shibata, Takanori Tsumura, Tomoaki Tsumura, Yasuhiko Nakashima. 1-8 [doi]
- Adaptive runtime management of heterogenous MPSoCs: Analysis, acceleration and silicon prototypeOliver Arnold, Gerhard Fettweis. 1-4 [doi]
- Implementation of Multicore communications APIJanne Virtanen, Lauri Matilainen, Erno Salminen, Timo D. Hämäläinen. 1-6 [doi]
- System on chip design of a linear system solverJiri Bucek, Pavel Kubalík, Róbert Lórencz, Tomás Zahradnický. 1-6 [doi]
- WOKE: A novel workflow model editorMikko Honkonen, Lauri Matilainen, Erno Salminen, Timo D. Hämäläinen. 1-8 [doi]
- Energy-efficiency of floating-point and fixed-point SIMD cores for MIMO processing systemsDaniel Günther, Andreas Bytyn, Rainer Leupers, Gerd Ascheid. 1-7 [doi]
- Fast Memory Region: 3D DRAM memory concept evaluated for JPEG2000 algorithmAlex Schönberger, Klaus Hofmann. 1-4 [doi]
- Constraint-driven frequency scaling in a Coarse Grain Reconfigurable ArrayWaqar Hussain, Henry Hoffmann, Tapani Ahonen, Jari Nurmi. 1-6 [doi]
- L2_ISA++: Instruction set architecture extensions for 4G and LTE-advanced MPSoCsOliver Arnold, Felix Neumaerker, Gerhard Fettweis. 1-8 [doi]
- Parallel and distributed simulation of networked multi-core systemsPhilipp Wehner, Diana Göhringer. 1-5 [doi]
- Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gatingKimiyoshi Usami, Makoto Miyauchi, Masaru Kudo, Kazumitsu Takagi, Hideharu Amano, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura. 1-7 [doi]
- Soft-core eFPGA for Smart Power applicationsMatteo Cuppini, Eleonora Franchi Scarselli, Claudio Mucci, Roberto Canegallo. 1-4 [doi]