Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture

Wim J. C. Melis, Shuhei Chizuwa, Michitaka Kameyama. Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture. In ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan. pages 233-238, IEEE Computer Society, 2009. [doi]

Authors

Wim J. C. Melis

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Shuhei Chizuwa

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Michitaka Kameyama

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