Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture

Wim J. C. Melis, Shuhei Chizuwa, Michitaka Kameyama. Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform and its VLSI Architecture. In ISMVL 2009, 39th International Symposium on Multiple-Valued Logic, 21-23 May 2009, Naha, Okinawaw, Japan. pages 233-238, IEEE Computer Society, 2009. [doi]

References

No references recorded for this publication.

Cited by

No citations of this publication recorded.