Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya. Gate level representation of ECL circuits for fault modeling. In First Great Lakes Symposium on VLSI, 1991, Kalamazoo, MI, USA, March 1-2, 1991. pages 330-331, IEEE, 1991. [doi]
Abstract is missing.