Modular Synthesis of Timed Circuits using Partial Order Reduction

Eric Mercer, Chris J. Myers, Tomohiro Yoneda. Modular Synthesis of Timed Circuits using Partial Order Reduction. Electronic Notes in Theoretical Computer Science, 65(6):180-201, 2002. [doi]

References

No references recorded for this publication.

Cited by

No citations of this publication recorded.