Parallel-pipelined architecture for 2-D ICT VLSI implementation - researchr publication bibtex

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Juan A. Michell, Gustavo A. Ruiz, Angel M. Buron. Parallel-pipelined architecture for 2-D ICT VLSI implementation. In ICIP (3). pages 89-92, 2003.

@inproceedings{MichellRB03,
  title = {Parallel-pipelined architecture for 2-D ICT VLSI implementation},
  author = {Juan A. Michell and Gustavo A. Ruiz and Angel M. Buron},
  year = {2003},
  tags = {architecture},
  researchr = {https://researchr.org/publication/MichellRB03},
  cites = {0},
  citedby = {0},
  pages = {89-92},
  booktitle = {ICIP (3)},
}

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