Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system - researchr publication authors

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Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka. Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system. In Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, Nippon Convention Center, Chiba, Japan, January 28-31, 1997. pages 329-332, IEEE, 1997. [doi]

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