Elham K. Moghaddam, Nilanjan Mukherjee 0001, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada. Logic BIST With Capture-Per-Clock Hybrid Test Points. IEEE Trans. on CAD of Integrated Circuits and Systems, 38(6):1028-1041, 2019. [doi]
@article{MoghaddamMRSTZ19,
title = {Logic BIST With Capture-Per-Clock Hybrid Test Points},
author = {Elham K. Moghaddam and Nilanjan Mukherjee 0001 and Janusz Rajski and Jedrzej Solecki and Jerzy Tyszer and Justyna Zawada},
year = {2019},
doi = {10.1109/TCAD.2018.2834441},
url = {https://doi.org/10.1109/TCAD.2018.2834441},
researchr = {https://researchr.org/publication/MoghaddamMRSTZ19},
cites = {0},
citedby = {0},
journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
volume = {38},
number = {6},
pages = {1028-1041},
}