A 748 GOPS/W RISC-V SoC with Reconfigurable Custom Instructions via a Synthesized eFPGA with 1.8µs Configuration Time in 22nm FinFET - researchr publication authors

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Prashanth Mohan, Siddharth Das, Ken Mai. A 748 GOPS/W RISC-V SoC with Reconfigurable Custom Instructions via a Synthesized eFPGA with 1.8µs Configuration Time in 22nm FinFET. In IEEE Custom Integrated Circuits Conference, CICC 2025, Boston, MA, USA, April 13-17, 2025. pages 1-3, IEEE, 2025. [doi]

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