Fast Buffer Count Estimation in 3D IC Floorplanning

Sucheta Mohapatra, Satya K. Vendra, Malgorzata Chrzanowska-Jeske. Fast Buffer Count Estimation in 3D IC Floorplanning. IEEE Trans. Circuits Syst. II Express Briefs, 68-II(1):271-275, 2021. [doi]

Authors

Sucheta Mohapatra

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Satya K. Vendra

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Malgorzata Chrzanowska-Jeske

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