Sucheta Mohapatra, Satya K. Vendra, Malgorzata Chrzanowska-Jeske. Fast Buffer Count Estimation in 3D IC Floorplanning. IEEE Trans. Circuits Syst. II Express Briefs, 68-II(1):271-275, 2021. [doi]
@article{MohapatraVC21,
title = {Fast Buffer Count Estimation in 3D IC Floorplanning},
author = {Sucheta Mohapatra and Satya K. Vendra and Malgorzata Chrzanowska-Jeske},
year = {2021},
doi = {10.1109/TCSII.2020.3007858},
url = {https://doi.org/10.1109/TCSII.2020.3007858},
researchr = {https://researchr.org/publication/MohapatraVC21},
cites = {0},
citedby = {0},
journal = {IEEE Trans. Circuits Syst. II Express Briefs},
volume = {68-II},
number = {1},
pages = {271-275},
}