Fast Buffer Count Estimation in 3D IC Floorplanning

Sucheta Mohapatra, Satya K. Vendra, Malgorzata Chrzanowska-Jeske. Fast Buffer Count Estimation in 3D IC Floorplanning. IEEE Trans. Circuits Syst. II Express Briefs, 68-II(1):271-275, 2021. [doi]

Abstract

Abstract is missing.