The complexity of VLSI power-delay optimization by interconnect resizing

Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. The complexity of VLSI power-delay optimization by interconnect resizing. J. Comb. Optim., 23(2):292-300, 2012. [doi]

@article{MoiseevKW12,
  title = {The complexity of VLSI power-delay optimization by interconnect resizing},
  author = {Konstantin Moiseev and Avinoam Kolodny and Shmuel Wimer},
  year = {2012},
  doi = {10.1007/s10878-010-9355-1},
  url = {http://dx.doi.org/10.1007/s10878-010-9355-1},
  researchr = {https://researchr.org/publication/MoiseevKW12},
  cites = {0},
  citedby = {0},
  journal = {J. Comb. Optim.},
  volume = {23},
  number = {2},
  pages = {292-300},
}