37.7 A 12.8Gb/s Parallel Receiver with a One-Way Self-Training Scheme for Equalizing ISI and Reflections in Multi-Drop Memory Interfaces

Ji-Won Moon, Taehyeon Kim, Minwook Kim, Hyeonwoo Seong, Jewon Lee, Jeongbin Park, Dongjun Park, Jaehoon Lee, Jung-June Park, Chiweon Yoon, Jae-Yoon Sim, Seon-Kyoo Lee. 37.7 A 12.8Gb/s Parallel Receiver with a One-Way Self-Training Scheme for Equalizing ISI and Reflections in Multi-Drop Memory Interfaces. In IEEE International Solid-State Circuits Conference, ISSCC 2026, San Francisco, CA, USA, February 15-19, 2026. pages 636-638, IEEE, 2026. [doi]

Abstract

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