A 1.8V 6-bit 1GS/s 60mW CMOS folding/interpolation ADC using folder reduction circuit and auto switching encoder

Junho Moon, Heewon Kang, Daeyoon Kim, Seungjin Yeo, Dubok Lee, Minkyu Song. A 1.8V 6-bit 1GS/s 60mW CMOS folding/interpolation ADC using folder reduction circuit and auto switching encoder. In 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008. pages 638-641, IEEE, 2008. [doi]

@inproceedings{MoonKKYLS08,
  title = {A 1.8V 6-bit 1GS/s 60mW CMOS folding/interpolation ADC using folder reduction circuit and auto switching encoder},
  author = {Junho Moon and Heewon Kang and Daeyoon Kim and Seungjin Yeo and Dubok Lee and Minkyu Song},
  year = {2008},
  doi = {10.1109/ICECS.2008.4674934},
  url = {http://dx.doi.org/10.1109/ICECS.2008.4674934},
  researchr = {https://researchr.org/publication/MoonKKYLS08},
  cites = {0},
  citedby = {0},
  pages = {638-641},
  booktitle = {15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julien's, Malta, August 31 2008-September 3, 2008},
  publisher = {IEEE},
  isbn = {978-1-4244-2181-7},
}